Optimizing InP HBT technology for 50 GHz clock-rate MSI circuits

Using experimental data and a sum of weighted RC time constant model we optimized AlInAs/GaInAs SHBT devices for minimum gate delay in a static divider. The best result obtained, a 55 GHz maximum clock rate, is to our knowledge the highest toggle rate reported to date. Comparable structures without critical base resistance optimization toggled at no more than 44 GHz. f/sub t/ and f/sub max/ were observed to be only weak indicators of divider performance. The calculated maximum toggle rates obtained from the weighted RC time constant method agree reasonably well with experiment. The experiments and analysis lead to the conclusion that the dominant parasitic component in this regime of ultra-high speed HBT is the base resistance.