An Ad-hoc IP Functional Verification Procedure

This paper presents an ad-hoc IP-verification proce dure that is used to verify the conformity between the IP specifications and their corresponding HDL-code implementation. The verification procedure is a genera l purpose solution offering an automatic validation to any IP design. The purpose of this paper is to provide a full desc ription of the verification procedure and how to tailor it in order to fit any particular needs. The Ad-hoc verification procedure has been used to validate several designed IPs, notably: FIFO, Trans ceiver and I 2 C-salve. The whole procedure code is implemented in both Verilog 2001 (IEEE 1365) and VHDL (2002).