Energy-efficient register file design

In this thesis, we evaluate five techniques for energy efficient register file design by studying dynamic traces of SPECInt95 and Powerstone benchmarks. A single-issue MIPS RISC microprocessor with a five-stage pipeline is used for this study. The five proposed techniques are precise read control, bypass skip, separate R0, modified storage cell, and split bitline. Their potential energy savings are examined through an energy dissipation model. On average, each technique shows 23%, 20%, 22%, 38%, and 20% respectively. An energy saving of 63% can be achieved by combining these five low power register file design methods without changing existing software. Thesis Supervisor: Krste Asanovic Title: Assistant Professor