An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation

In this paper, we propose an ultra-low-voltage (ULV) SRAM in 28nm FDSOI based on a 7-T ULP bitcell that allows using only low V t (LVT) transistors for density and speed without prohibitive leakage. The retention is based on two CMOS negative-differential resistance (NDR) structures. Thanks to importance sampling (IS) methodology, the proposed bitcell has been sized to reach low failure rate for 8-kB macro. Process voltage temperature (PVT) compensation is performed on-chip by an adaptive back biasing (ABB) generator. At 0.4V, the proposed SRAM can operate at 80 MHz and reaches access energy of 28 fJ/bit including the ABB generator in closed-loop operation.