High-speed high-jitter-tolerance random-data linear phase detector circuit

The invention discloses a high-speed high-jitter-tolerance random-data linear phase detector circuit. The prior random-data linear phase detector circuit consists of two triggers and two exclusive-OR gates, wherein the two exclusive-OR gates characterize error signals of the phase difference of output clock and input data and characterize ref signals of the jump density of the input data respectively, and as the triggers have time delay, the error signals and the ref signals are not equal or synchronous in pulse width when the rising edge of the clock is in alignment with the very middle of the position of the input data. The circuit of the invention is provided with a time-delay matching unit and a latch on the basis of the prior linear phase detector circuit, and splits a D trigger into two cascaded latches, thereby solving the problem that the error signals and the ref signals are not equal or synchronous in the pulse width, effectively increasing the jitter tolerance of the input data, reducing the jitter of output signals and applying to high-speed systems at a speed above GHz.