Method for manufacturing VLSI complementary MOS field effect transistor circuits in silicon gate technology

Complementary MOS field effect transistor circuits are produced in silicon gate technology, with the method steps up to the structuring of the gate electrode being executed in a known manner. Both source/drain implantations (FIG. 3, 8 and FIG. 5, 10) occur with only one mask (7a). This mask (7a), which is composed of silicon nitride, is utilized for the source/drain implantation 8 of the n-channel transistors (9). The source/drain implantation (10) for the p-channel transistors (11) occurs without a mask and the oxide layer thickness, d6, over the source/drain regions of the n-channel transistors (9) functions as a masking layer. An advantage of this process sequence is that switched capacitor structures (FIG. 6, 5b, 12) can be simultaneously produced whereby the oxide layer thickness, d4, over the polysilicon-1 level (5a, 5b) determines the thickness of the insulating layer, dcox, of the capacitor structures (5b, 12). This technique is useful for manufacturing VLSI CMOS circuits in VLSI technology with and without switched capacitors.