A cost effective test screening method on 40-nm 4-Mb embedded SRAM for low-power MCU

An embedded single-port SRAM with cost effective test screening circuitry is demonstrated for low-power micro controller units (MCUs). The probing test step at low-temperature (LT) of −40°C is eliminated by imitating pseudo LT conditions in the final test step where a sample is measured at room temperature (RT). Monte Carlo simulation is carried out with consideration of global and local Vt variations as well as contact soft open failure (high resistance), confirming good Vmin correlation between LT and pseudo LT conditions. Test chips with a 4-Mbit SRAM macro are designed and fabricated using 40-nm low-power CMOS technology. Measurement results show that the proposed test method can reproduce LT conditions and screen out low temperature failures with less overkill.