Graphene-Based on-Chip ESD Protection

Electrostatic discharge (ESD) failure is a devastating IC reliability problem. Traditional in-Si PN-junction based on-chip ESD protection structures are becoming unsuitable to IC at advanced technology nodes due to ESD-induced parasitic effects and layout issues [1–3]. On-chip ESD protection for future chips calls for revolutionary solutions. This paper reviews recent advances in developing graphene-based ESD protection structures including systematic and statistical transient ESD characterization of graphene ribbons (GR) as possible ESD interconnects [4] and graphene nano-electromechanical system (NEMS) ESD protection structures [3, 5]. The novel graphene-based ESD protection concept shows the potential for future chips.