Layout and spacer optimization for high-frequency low-noise performance in HBT's

In this work we study improvements of the high-frequency noise performance of HBT devices by means of layout and spacer optimization. Using an equivalent circuit, we identify the dominant noise sources and demonstrate that the reduction of the base-resistance induced thermal noise by means of dotted emitters in combination with lowering the edge contribution of the base-emitter capacitance (e.g. by emitter-base spacer optimization) translates into better noise performance.