Commercially developed mixed-signal CMOS process features for application in advanced ROICs in 0.18μm technology node
2012
Increasingly complex specifications for next-generation focal plane arrays (FPAs) require smaller pixels, larger array
sizes, reduced power consumption and lower cost. We have previously reported on the favorable features available in
the commercially available TowerJazz CA18 0.18μm mixed-signal CMOS technology platform for advanced read-out
integrated circuit (ROIC) applications. In his paper, new devices in development for commercial purposes and which
may have applications in advanced ROICs are reported. First, results of buried-channel 3.3V field effect transistors
(FETs) are detailed. The buried-channel pFETs show flicker (1/f) noise reductions of ~5X in comparison to surface-channel
pFETs along with a significant reduction of the body constant parameter. The buried-channel nFETs show ~2X
reduction of 1/f noise versus surface-channel nFETs. Additional reduced threshold voltage nFETs and pFETs are also
described. Second, a high-density capacitor solution with a four-stacked linear (metal-insulator-metal) MIM capacitor
having capacitance density of 8fF/μm 2 is reported. Additional stacking with MOS capacitor in a 5V tolerant process
results in >50fC/μm 2 charge density. Finally, one-time programmable (OTP) and multi-time programmable (MTP) non-volatile
memory options in the CA18 technology platform are outlined.
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