Characterization of Single-Poly SGLC Cell Using 4kbits Array Test Chip for a Low Density Code Storage Embedded NVM Applications

In this paper, we have evaluated select gate lateral coupling (SGLC) cell by using a 4kbits (kb) macro. Using large data cell VT distributions, tail bit behavior can be analyzed. The test chip is fabricated on a 90 nm high voltage CMOS process without any additional steps. Thanks to the unique lateral coupling operation method, the size of the SGLC cell is comparable to SRAM of the same technology node resulting in the smallest single-poly non-volatile memory (NVM) cell size of 1.34 μm2 at 90 nm technology node. However, because of the high aspect ratio of unit cell geometry of 3.28 : 1, it was difficult to arrange word-line and bit-line decoder efficiently. For the 4-kb SGLC cell macro, by structuring the top and bottom side located cell addressing decoders, we achieved efficient decoder architecture and further memory density extension capability. Through the 150 oC retention bake test, we analyzed the possible retention weak cells that may be generated by the silicide-FG structure. As a result, over 10-years lifetime for code storage applications is verified without tail bit occurrences.