A 2ps minimum-resolution, wide-input-range time-to-digital converter for the time-of-flight measurement using cyclic technique and time amplifier

A new time-to-digital converter (TDC) for the time-of-flight measurement (TOF) architecture using a cyclic method and time amplifier (TA) with three level conversions is proposed. To increase the input range of the TDC and protect it from PVT variations, the cyclic method and DLL architecture are used in a second-level conversion. The third conversion calculates the residue remaining after the second conversion as a combination of the Vernier delay line (VDL) and TA in order to implement high resolution. Through the combination of VDL and TA, the area is reduced compared with the single VDL. The proposed TDC has been implemented and simulated in a 65-nm CMOS process with an active core size of um 0.22 mm2. The input range is over 1p, and the minimum time resolution is 2ps with a core power consumption of 69.7 mW.