Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solution

abstract This work proposes a planar fully depleted ‘‘folded” technology integrated on bulk substrate as an inno-vative solution for upcoming low power nodes to enhance drive current on narrow devices. We report adetailed fabrication method, combining advanced selective epitaxy faceting and SON (Silicon-On-Noth-ing) process, to provide ultra thin body and buried oxide (UTB 2 ) devices with improved drive currentI on for a given designed footprint W design when scaling the device width. We compare the fabricationand electrical behavior between h110i channel, i.e. 0 -rotated wafer, and h100i channel, i.e. 45 -rotatedwafer, for the same (1 0 0) surface orientation. 2009 Elsevier Ltd. All rights reserved. 1. IntroductionBeyond the performance improvement through the scaling the-ory [1], device active area W L reduction is fairly known to be amajor concern for increasing density integration and thus reducingmass production cost. Usually the interest for narrow channel isimpeded by the diminution of transconductance gain b =