Designing mega-ASICs in nanogate technologies

This paper discusses challenges the designer faces in integrating entire system product designs, containing tens or even hundreds of millions of logic gates, into single chip solutions now within reach using circuit densities possible in the latest silicon technologies. Managing designs of this size presents a new dimension of issues, and managing the physical and electrical effects of these high density device geometries presents another; solutions in both these areas are presented. Lastly, this paper discusses the integration of multiple functional components (previously organized as systems of multiple chips from multiple design sources and technologies) into a single chip product.