A 576-Mbit/s 64-QAM 4 $\times$ 4 MIMO Precoding Processor With Lattice Reduction

This brief presents a lattice reduction (LR) aided precoding processor for 64-QAM 4 × 4 multiple-input-multiple-output systems. The proposed processor is based on a modified Lenstra-Lenstra-Lovasz LR algorithm and the Tomlinson-Harashima precoding (THP) algorithm. This study develops a configurable architecture for high-throughput THP processing or high-performance LR-THP processing. The proposed processor can also change the stage number of the LR algorithm to achieve a tradeoff between performance and throughput. This study designs and implements the precoding processor by using TSMC 90-nm 1P9M CMOS technology. The chip measurement results presented in this study show that the proposed processor achieves 576 Mbit/s in the THP mode or 10 -3 bit error rate in the LR-THP mode with 64-QAM modulation at 28.3 dB. The chip occupies a 0.5- mm 2 area and consumes 15.4 mW of power at its maximum clock speed of 120 MHz.