Gate Current Cancellation Using a Replica PMOS and Digital Feedback for Temperature-coefficient Reduction on an Ultra-low Power Voltage Reference

A method to cancel the gate current loading at the output of ultra-low power voltage references using a replica PMOS and digital feedback is proposed, reducing the achieved temperature coefficient (TC). A time-based ultra-low power gate current-to-digital circuit, which takes advantage of an inherently infinite current-controlled oscillator (CCO)-based integrator gain to sense picoamperes of gate current, and an intrinsically low-bandwidth sensed gate current, is implemented. In addition, the practical and the fundamental limitation on the maximum achievable resolution of the gate current sensor is derived. Furthermore, a new figure of merit (FOM) for ultra-low power voltage references is proposed, which considers not only their power consumption and TC, but also the value of its load current.