Hetero-Dielectric oxide engineering on dopingless gate all around nanowire MOSFET with Schottky contact source/drain

Abstract In proposed work, gate oxide engineered Schottky Barrier (SB) Hetero-Dielectric (HD) Single Metal (SM) Gate All around Nanowire MOSFET is purposed for low power digital circuitry. Proposed device has an asymmetric oxide geometry having high-k (HfxTi1-xO2) on source side and SiO2 on drain side with Schottky Source/Drain regions. Leakage currents are reduced to an order of 10−15 over 10−9 A as compared to conventional GAA MOSFET. Device is simpler in fabrication in contrast to Junctionless (JL) NWFETs due to its dopingless design. Also, it has almost negligible gate induced drain leakage (GIDL) current value. An extensive comparison is outlined between the subthreshold performance of Single metal, Dual metal Hetero-Dielectric (HD) and Gate Stack (GS) SB-SM-GAA NWFET configurations. An improvement is observed in ON to OFF-state current ratio by 68.05% and an impressive decline in drain induced barrier lowering (DIBL) by 48.15% in HD-SB-SM-GAA NWFET as compared to Gate stack structure at same physical dimensions. Further, SM device has been found to have better ION/IOFF ratio, higher transconductance, lowered DIBL and an optimum subthreshold slope as compared to DM device.