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Topology Optimization of 3D-Stacked Chips under Maxiumum Wire Length Constraint
Topology Optimization of 3D-Stacked Chips under Maxiumum Wire Length Constraint
2015
Nakahara Hiroshi
Fujiki Daichi
Tade Seiichi
Yasudo Ryota
Kawano Ryuta
Matsutani Hiroki
Koibuchi Michihiro
Nakano Koji
Amano Hideharu
Keywords:
Topology optimization
Engineering drawing
Electronic engineering
Computer science
Topology
Correction
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