Effect of local interconnect etch-stop layer on channel hot-electron degradation

Routine use of an etch-stop layer during semiconductor processing favors circuit density and performance throughthe use of local interconnect and similar damascene processes, and also allows the use of manufacturable etchrecipes. Previous studies have demonstrated that post transistor definition, topside passivation and depositiontechniques can significantly impact device degradation characteristics. This work further investigates the choice oflocal interconnect etch-stop layer and its effect on channel hot-electron degradation. A reduction in channel hot-electron degradation is demonstrated through the use of N20 anneal gate oxide, and using experimental data apossible degradation mechanism, caused by the presence of the etch-stop layer, is identified. A brief review of thecompatibility of etch-stop layers with high performance O.3im CMOS devices is presented through interface stateand hot-electron stress measurements.Keywords: hot-electron, local interconnect, damascene, SiN.