Design of Low Power Multiplier for Vision chips

With the popularity of pruning operations in neural networks, the percentage of zero-operands in mainstream neural network computing is getting higher. To meet the low-power requirements of neural network computing, the zero-skipping operation in multiplication is used in deep learning computing. This paper proposes a zero-skipping design of low-power multiplier for vision chips, which reduces the power consumption of the arithmetic and logic unit (ALU) by up to 32%, of which the low power consumption effect is remarkable.