Measurement and analysis of SiC-MOSFET threshold voltage shift

Abstract Silicon carbide power MOSFETs are used in numerous studies to improve the efficiency or the performance of power electronic converters. However, the gate-oxide technology weakness is a main reliability issue of silicon carbide MOSFET transistors. The threshold voltage shift is a critical phenomenon that addresses the reliability of industrial power applications. It is important to have a better understanding of the phenomena implied in the gate threshold voltage shift. In this context, a static ageing test based on JEDEC standard is proposed and the resulting gate oxide stress is studied and discussed in this paper. Complementary testing was performed with dynamic reliability and gate oxide characterizations, such as the charge pumping technique. The results obtained are used to add insight to the current discussion of SiC MOSFET robustness. Additionally test benches and measurement protocols established on 1.7 kV 45 mΩ are detailed, which will be useful for the next generation of SiC MOSFET.