A manufacturable copper/low-k SiOC/SiCN process technology for 90 nm-node high performance eDRAM

In this paper, we describe the Cu/low-k (k < 3) dual-damascene process integration targeting for 90 nm-node (0.28 /spl mu/m pitch) high performance embedded DRAM devices. A stable and well-controlled dual-damascene structure was realized both by using newly developed stacked mask process (S-MAP) and a low-damage resist ashing process. Problems and solutions for resist poisoning due to the stopper-SiCN layer and capping-SiO/sub 2/ layer are investigated. We also demonstrated a notable via chain yield (with 2.9 M vias) by applying low-k PE-CVD SiOC/SiCN dielectrics.