High speed low power Full Adder circuit design using current comparison based domino

In this paper, a new Full Adder circuit is designed using current comparison based domino logic style, which has a lower leakage and higher noise immunity along with high speed. This circuit achieved high speed and better noise immunity by reducing the parasitic capacitance on the dynamic node, yielding a keeper in the pull up network. The leakage current is reduced by introducing a transistor in diode configuration. The full adder circuit is simulated in 0.12μm CMOS technology with V DD =1.2V. The total average power dissipation is 24μw at temperature T=120°C with a layout area of 116μm 2 The total capacitance at the dynamic node is computed as 8fF from the layout and this capacitance includes all the parasitic capacitances associated with the dynamic node.