Ultra Low Power Circuit Design

Abstract In many new high performance designs, the leakage component of power consumption is comparable to the switching component. Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase at nano-regime with technology scaling unless effective techniques are introduced to bring leakage current under control. This paper focuses on various techniques to reduce leakage current at 45 nm CMOS technology using cadence tool.