Implement of time division multiplexing high speed programmable Viterbi decoder IP core

The programmable Time Division multiplexing high Viterbi decoder IP core is studied in this paper. According to the characteristics of multiple communication system, the method of programmable time-division multiplexing is puts forward, the high-performance and less resource occupy IP core is designed. Based on SMIC 0.18um CMOS technology, the ASIC of IP core is test. The test results show that the IP core areas, power and frequency could satisfy demand of real-time communication.