Study of process contributions to total overlay error budget for sub-60-nm memory devices

According to the 2006 International Technology Roadmap for Semiconductors, the overlay budget of 60nm memory devices is 11nm. To meet such a tight requirement, the total overlay error budget should be controlled carefully. There are many ways to analyze overlay budget; here, however, a simple but accurate methodology is introduced. In this study, total overlay error budget consists of four major contribution categories: scanner, process, metrology, and mask contributions. Scanner contributions are evaluated by measuring machine-to-machine overlay errors in the conventional way. Process contributions are estimated by inverse reactive-ion etch (RIE) lag and chemical mechanical polishing (CMP) erosion. Metrology contributions are evaluated by overlay metrology tools. Finally, mask contributions represent mask-to-mask misregistration. By applying this methodology to 60nm memory devices, it turns out that process contributions are more than 30% of the total overlay error budget for a contact layer. In this art...