f T Improvement of RF CMOS Transistor in Circuit-Level by Layout Optimization

In this paper, $f_{T}$ improvement of radio-frequency (RF) CMOS transistor in circuit-level by layout optimization has been presents. A new layout optimization scheme to reduce the interconnect parasitic of multi-finger MOSFETs is present in this paper. The devices characterized are simulated by a 55-nm RF CMOS process model. The post-simulation shows that the $f_{T}$ performance improves 24.4% at 80GHz. And the proposed optimization of the RF MOS layout can significantly improve the S21 and NF characteristics of the low noise amplifier (LNA).