A novel method to form nano-gridlines on textured CZ silicon wafers

We report a novel method to form metal nano-gridlines on textured Czochralski (CZ) silicon. This involves the deposition of tensile stressed silicon nitride under conditions that cause cracks at the base of the pyramid features. The crack width is adjusted with buffered BHF and the opening is self-aligned with the nitride as a mask. Subsequently, the metal lines are plated within the cracks, forming conductors with submicron dimensions. The metal grid provides a conduction path parallel to the emitter, relaxing sheet resistance requirements for a diffused emitter.