A 133 MHz 64 b four-issue CMOS microprocessor

1995 
This superscalar microprocessor is the first 64 b implementation of the PowerPC architecture. With estimated performance levels of 225 SPECint92 and 300 SPECfp92 at a nominal processor frequency of 133 MHz and a 4ML2 operating at 67 MHz, this processor delivers balanced performance suitable for high-end workstations and servers. The chip is realized in n-well 0.5 /spl mu/m CMOS with p-epi on a p/sup +/ substrate. There are four layers of metallization. The processor contains 6.88M transistors and dissipates an estimated 30 W at 133 MHz from a 3.3 V power supply. The 18.2/spl times/17.1 mm/sup 2/ die is packaged in a 25/spl times/25 ball grid array.
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