Integrated circuit semiconductor device having different impurity concentration in respective regions of a semiconductor wafer, and fabrication method thereof

An integrated circuit semiconductor device of the present invention, the central region, but by the middle area and edge area each comprise a semiconductor wafer having a different concentration of impurities, the central region has an impurity concentration higher than the middle area, the middle area is the edge area the more the semiconductor wafer including a large impurity concentration. A gate of this invention is formed on a semiconductor wafer comprising a central region, the intermediate region and the length of the other gate pattern by the edge of the semiconductor wafer, the length of the gate pattern is formed in the central region is formed in the middle area smaller than the length of the pattern, the length of the gate pattern formed on the intermediate region is characterized by less than the length of the gate pattern formed on the edge region. Accordingly, the invention may take a uniform threshold voltage on a semiconductor wafer.