Thermal Noise-Induced Error Simulation Framework for Subthreshold CMOS SRAM

Accurate error-rate modeling in ultra-low-power subthreshold CMOS circuitry is needed to predict reliability. In this study, we extend our stochastic time-domain error simulation framework to thermally-induced bit-flip errors in ultimate CMOS SRAM cells. Our approach extracts the dependence of error rate on technological parameters such as operating voltage, threshold variability, and temperature. Our analysis tool extracts behavior that cannot be captured with conventional SPICE-based simulations and provides the first statistically rigorous tool for evaluating ultimate SRAM reliability.