Self-Aligned Enhancement-Mode and Parasite Depletion-Mode Heterojunction Doped-Channel FET for Low Power Supply DCFL Application

We demonstrate that a heterojunction doped-channel field-effect transistor (HDCFET) structure, using an additional p + -GaAs cap layer, simultaneously obtains both p-n junction and Schottky junction to fabricate the enhancement mode and depletion mode of HDCFET (EHDCFET and DHDCFET) on the same chip, thus implementing a direct-coupled field effect transistor logic (DCFL) circuit. In addition, an additional p + -GaAs cap layer can perform controllable undercut profile with wet etching to proceed with self-aligned technology resulting in a T-shaped gate structure. The microwave characteristics have also been investigated. The cutoff frequency of the E/D inverter (EDI) is nearly the same with the self-aligned EHDCFET for varied gate-source voltage. When V GS = 0.7 V, the cutoff frequency for three self-aligned EHDCFET, parasitic DHDCFET, and EDI are 16.8 GHz, 9.8 GHz, and 17 GHz, respectively. The self-aligned EHDCFET dominates the EDI electrical performances. Furthermore, the better inverter performances, the logic-low noise margin and logic-high noise margin, are found to be 260 mV and 360 mV, respectively.