Lead‐free solder joint reliability estimation of flip chip package using FEM‐based sensitivity analysis

Purpose – Integration of Cu/low‐k interconnects into the next‐generation integrated circuit chips, particularly for devices below the 90 nm technology node, has proved necessary to meet the urgent requirements of reducing RC time delay and low power consumption. Accordingly, establishment of feasible and robust packaging technology solutions in relation to the structural design, as well as material selection of the packaging components, has become increasingly important. Moreover, the nature of low‐k materials and the use of lead‐free solder greatly increases the complications in terms of ensuring enhanced packaging level reliability. The foregoing urgent issue needs to be quickly resolved while developing various advanced packages. This paper aims to focus on the issues.Design/methodology/approach – The prediction model, especially for the fatigue life of lead‐free solder joints, combined with virtual design of experiment with factorial analysis was used to obtain the sensitivity information of selecting...