FPGA-Based Echo-State Networks

The hardware implementation of Echo State Networks (ESN) can be applied to situations where a quick response is needed in relation to how a certain signal will evolve. This is due to the possibility of connecting the ESN’s neurons in parallel, which accelerates the calculation process considerably. In this article, we present a proposal for the compact implementation of ESN in Field Programmable Gate Arrays (FPGAs). To maximize the number of neurons, the synapses are implemented using adders and multiplexers instead of multipliers. The hardware implementation has been tested for the prediction of the Santa Fe time-series dataset. The proposed approach allows for significant savings in terms of energy, hardware resources, and computing time compared to other recently published solutions.