Automation of Domain-specific FPGA-IP Generation and Test

Multi-access edge computing (MEC) devices that perform processing between the edge and cloud are becoming important in the Internet of Things infrastructure. MEC devices are designed to reduce the load on the edge devices, ensure real-time performance, and reduce the communication traffic between the edge and cloud. In this paper, to enable high-performance and low-power hardware-accelerated processing for different application domains in MEC devices, we propose an automated flow for domain-specific field-programmable gate array intellectual property core (FPGA-IP) generation and testing. First, we perform logic cell exploration using a target user application to find the optimal scalable logic module (SLM) structure, and use the optimal SLM instead of a lookup table to reduce the logic area. Second, we perform routing and FPGA array exploration to determine other FPGA-IP architecture parameters. Finally, the proposed flow uses the explored parameters to automatically generate the entire FPGA-IP and LSI test bitstreams. In a case study, we optimized an FPGA-IP for a differential privacy encryption circuit using the proposed flow. We implemented and evaluated the FPGA-IP with a 55nm TEG chip design. Furthermore, the simulation-based LSI test showed that 100% of the stuck-at faults in the routing paths of the FPGA-IP were detected.