8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm

The proliferation of hyperscale data centers, as well as edge and 5G infrastructure build-outs, requires SerDes running at different rates, over different insertion losses, and in different environments. This work presents a scalable ADC/DSP-based transceiver architecture that runs from 1.25Gb/s NRZ to 56Gb/s PAM-4 in 16nm, supporting channels from very short reach (VSR) at 10dB to long reach (LR) above 35dB. A follow-on design supports 1.25Gb/s NRZ to 112Gb/s PAM-4 in 7nm, and its measured results are also presented in this paper. Some of the key architectural features and innovations that will be described in the paper are: a single decision-feedback equalizer (DFE) with minimum mean square error (MMSE) criteria to drive all feedback control loops, including (i) decision-directed MMSE (DD-MMSE) clock and data recovery (CDR), (ii) feed-forward equalization/decision-feedback equalization (FFE/DFE) bit-error rate (BER) optimization, and (iii) time-interleaved ADC (TI-ADC) clock skew correction.