A 0.01mm 2 4.6-to-5.6GHz sub-sampling type-I frequency synthesizer with −254dB FOM

Power consumption, Performance in terms of phase noise and integrated jitter, and Area (PPA) are three design metrics that have driven countless research efforts in CMOS frequency-synthesizer design. Design limitations and system-level tradeoffs have made simultaneous optimizations of PPA metrics in PLLs challenging. In traditional Type-II charge-pump (CP) based PLLs, power is consumed in the VCO, divider (N), and CP to improve noise performance, and area is consumed in large loop-filter (LF) capacitors. ADPLLs are attractive due to compact LF, but are limited in noise performance. Sub-sampling (SS) PLLs eliminate divider noise, and remove the N 2 amplification of the phase detector (PD), CP, and LF noise, thereby improving the overall phase-noise performance [1]. However, their area is large due to the LF capacitors [1]. The performance of CPs and ring-VCOs in traditional or SS Type-II PLLs are also encumbered by reduced V DD in scaled CMOS processes. Overall, PLLs with ring-VCOs have higher noise [2,3], and PLLs with LC-VCOs have larger area [1]. Figure 15.6.1 highlights the PPA tradeoffs in prior art.