Modélisation de haut niveau de systèmes intégrés et estimation de performances : application à une implémentation multi-processeurs de la couche physique d’une station de base LTE

The impressive advances in both fields of semiconductors and software engineering enabled modern System-on-Chip “SoC“ to hostcomplex and interdependent applications. These advances are coupled with higher systems complexity and heterogeneity. Thus, forcing designers to re-evaluate their design methodologies and to raise the level of abstraction to the system level targeting the co-design of the entire SoC rather than just individual components. The objective of this Thesis work is to provide the system designer with means (on the methodology and tools levels) to estimate system’s performances and evaluate rapidly and very early the design decisions in the SoC design flow. Our work provides contributions in two main aspects: (1)On the Conceptual Level, we defined (using the UML meta-modeling concepts) modeling concepts to estimate shared resources impact on system’s overall performances, by introducing the “virtual node” concept for scheduling and shared resources access control. Furthermore, we introduced the ”Communication Pattern” concept for modeling the interaction between architecture elements to ensure the orthogonalization of computation and communication concerns. (2)On the Simulation Level: A SystemC simulator was written to simulate the UML models. Simulation is done at a high level of abstraction and runs faster than real time execution. The usability and capabilities of our approach are shown with an industrial use case. We modeled a Freescale multi-core DSP platform for LTE base stations (LTE stands for Long Term Evolution is the 4G standard for cellular networks). The comparison of modeling results with implementation proved the accuracy of our approach.