Design of the high speed RS decoder based on FPGA

The design proposal of the RS(255,223) high speed decoder based on RiBM algorithm is put forward,and the decoder is implemented with FPGA and Verilog HDL.The decoder has advantages of high decoding speed and occupancy less hardware resources,which is realized with three-level pipeline structure and the module of key equation solution is implemented with RiBM algorithm.The simulation result validates the validity and feasibility of the design proposal of the decoder.