Gross delay defect evaluation for a CMOS logic design system product

Randomly occurring gross delay defects allow chips to pass full stuck-fault testing at both wafer and module levels, but cause them to fail when operated at system speeds. This paper describes the results of an experiment designed to determine the actual delay defect component of shipped product quality level (SPQL) for a CMOS combination standard cell/gate array design system. More than 60,000 modules, representing chips from the same IBM computer system, have been delay-tested using the technique presented in this paper. The test technique uses the stuck-fault patterns for level-sensitive scan design (LSSD) product. The stuck-fault patterns are modified or “twisted” according to specific algorithms to propagate transitions through paths just prior to the output measure. The patterns are applied at system speed timings provided by the chip designers. Any gross delay defect present in a tested path causes a fail. The failing modules were characterized to determine the size of the delay defects. Failure diagnostics were performed on the defective modules by using existing stuck-fault diagnostic tools and a development version of a transition fault simulator. These were sent to physical failure analysis for delayering, visual verification, and electrical characterization. A summary of physical defects which produced gross delay defects is presented.