Important challenges for line-width-roughness reduction

It is supposed that double patterning process is one of the promising candidates for making mask pattern for dry etching at 32nm and 22nm node. Currently, drastic improvement of overlay of scanner is considered to be the most important challenge and much attention has been paid to sidewall spacer process since it can avoid that problem and also can provide easier method to fabricate patterns repeatedly. In this paper, material option of core pattern, spacer pattern and hard mask, which are main components of this process, is presented and 32nm gate pattern is actually fabricated after process optimization. In addition, line-width-roughness (LWR), whose reduction is becoming more and more necessary, is measured in each process step of spacer process.