A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction using Dual-Page Operation

Emerging memory-intensive applications require a paradigm shift from processor-centric to memory-centric computing. The performance of state-of-the-art computing systems and accelerators designed for such applications is not limited by the processing speed but rather by the limited DRAM bandwidth and long DRAM latencies. Although, the interface frequency of new commodity DRAM memories is constantly increasing to achieve a higher peak bandwidth, this bandwidth cannot be fully utilized due to long internal latencies. Page-misses (i.e., change of active row) are one of the key contributors to long access latencies that result in a low bandwidth utilization. In this brief, we propose a novel DRAM sub-array level architecture referred to as Dual-Sense-Amplifier (DSA) that masks the page-miss latency by allowing individual sub-arrays or banks to flexibly open two rows concurrently. Additionally, the DSA architecture design aim to be fully compatible with any type of commodity DRAM architecture (e.g., HBM, GDDR, etc.) and to retain most of its circuit designs. The area overhead of DSA for an 8Gb device is 9.6% compared to a commodity DRAM device. On average, a DSA 8Gb device improves the bandwidth utilization by 17.53% and reduces the average response latency by 31.59 ns compared to commodity DRAM devices operated at 800 MHz. Moreover, we demonstrate that the energy consumption overhead of a DSA DRAM in comparison to a commodity DRAM is negligible.