一個時脈為1 GHz訊號頻寬50 MHz之十一位元連續時間積分三角調變器

Oversampling sigma delta (ΣΔ) ADCs are widely used in application-specific ICs due to their high dynamic range and low power consumption. It is feasible to build high resolution continuous time sigma delta ADCs with bandwidth up to tens of MHz due to non-sampling loop filter, leading to more power and area efficient ADCs. In this thesis, a power-efficient continuous time sigma delta modulator (CTSDM) with 50 MHz signal bandwidth implement in TSMC 90 nm CMOS process. To realize such application scenario, the proposed CTSDM comprises a fifth-order loop filter with an active-RC integrator and two single op-amp resonator, and a 4-bit internal quantizer operating at 1 GHz clock frequency. To reduce clock jitter sensitivity, non-return-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and compensation is achieved by the DAC directly feedback to quantizer input. The proposed CTSDM achieves SNDR equal 68 dB (ENOB 11-bits) over a 50 MHz signal bandwidth. The power consumption is 89.9 mW from a 1 V supply and the energy per conversion is 434.1 fJ from post-layout simulation.