A 1.72μW, 23.2fj/conversion step successive approach ADC for bio-medical signal acquisition

This paper presents a successive approach register (SAR) analog-to-digital converter (ADC) with a novel hybrid digital-to-analog converter (DAC) architecture: half junction splitting (J.S.) and half binary weighted capacitor DAC. This DAC maintains low power consumption of J.S. DAC and the high signal-to-noise plus distortion ratio (SNDR) of binary weighted capacitor DAC. The power dissipation of the circuit is 1.72μW, SNDR 59.17dB, spurious free dynamic range (SFDR) 73.39dB, and the FOM 23.2fj/conversion step with 0.9V supply voltage. The proposed circuit is fabricated in TSMC 0.18μm 1P6M CMOS process technology.