A Hardware System for Fast AER Object Classification with On-chip Online Learning

This paper proposes a customized VLSI system for fast address-event representation (AER) object classification based on simple random ferns. The system architecture maximizes data throughput by employing circuit pipelines, while minimizing chip resource cost by allowing the datapath to be dynamically reused for both class inference and online learning procedures. The extra time consumed for learning on the chip is negligible. An FPGA prototype of the proposed system was implemented. It can process up to 100 million AER spikes per second and achieves 77.2% classification accuracy on the MNIST-DVS dataset.