Comparative Analysis of Adiabatic Logic Techniques

Power Consumption being the prime concern of VLSI designers has always been the source of motivation behind today‟s VLSI state of the art. Adiabatic technique is an emerging field promising significant reduction in the power consumption of the chip. Among several existing techniques, exhaustive comparison is made between SCRL, ECRL and PFAL techniques. The performance of each circuit is studied in terms of the maximum frequency of operation, area overhead over its conventional counterpart and the circuit energy consumption with different load capacitance. Power measured for adiabatic logic techniques and conventional CMOS circuit shows substantial difference in values. Circuit simulation is carried out in LTSPICE.