A flexible heterogeneous hardware/software solution for real-time high-definition H.264 motion estimation

The MPEG-4 AVC/H.264 video compression stan- dard introduces a high degree of motion estimation complexity. Quarter-pixel accuracy and variable block-size significantly en- hance compression performances over previous standards, but increase computation requirements. Firstly, a DSP-based solu- tion achieves real-time integer motion estimation. Nevertheless, fractional-pixel refinement is too computationally intensive to be efficiently processed on a software-based processor. Secondly, to address this restriction, a flexible and low complexity VLSI sub-pixel refinement coprocessor is designed. Thanks to an improved datapath, a high throughput is achieved with low logic resources. Finally, we propose a heterogeneous (DSP-FPGA) solution to handle real-time motion estimation with variable block-size and fractional-pixel accuracy for high-definition video. It combines efficiency and programmability. The flexibility offers complexity versus performance trade-offs. The system achieves motion estimation of 720p sequences at up to 60 frames per second. Index Terms—Field programmable gate arrays, Digital signal processors, Motion estimation, Parallel processing, Real-time, H.264