Total-dose tolerance of a chartered semiconductor 0.35-/spl mu/m CMOS process

MOSFETs fabricated in the commercial Chartered Semiconductor 0.35-/spl mu/m CMOS process were characterized with respect to the effects of total dose irradiation. Gate oxide threshold voltage shifts at 100 krad(Si) for both minimum geometry 0.70/0.35 NMOS and PMOS transistors biased for worst-case shifts were less than 20 mV. Off-state field leakage currents for isolated NMOS transistors were below 10 nA at 100 krad(Si), but became large at 300 krad(Si). The effect of a post-irradiation high temperature anneal was to lower these leakage currents to less than 100 pA. PMOS transistors exhibited less than 10 pA leakage for doses up to 300 krad(Si). Measurements on edgeless annular NMOS transistors showed no significant increase in leakage current with total dose, indicating that the increased leakage observed in standard NMOS transistors is the result of field leakage associated with inversion in the bird's beak region at the transistor/field oxide interface. C-V measurements on field-oxide capacitors over substrate biased for worst-case threshold voltage shifts showed the capacitors did not invert at 100 krad(Si) for 3.3 V operation. Measurements on ring-oscillators biased dynamically during irradiation showed no significant change in the gate delay or power up to 300 krad(Si) total dose, suggesting that for actual digital circuits applications, functionality and performance may be able to be maintained to doses substantially above 100 krad(Si).