Complementary sidewall-spacer-diffused ultrashallow SD extension process for damascene independently-double-gated SOI CMOS

We introduce a new SOI CMOS device, Flexfet/sup TM/, that utilizes a gate trench etched through thick implanted SD regions to self-align a hyper retrograde implanted bottom gate with a metal top gate, and create an ultra-thin channel region. Rapid thermal diffusion from complementary PSG/BSG sidewall spacers was used to achieve 15 nm USJ SDEs that connect to deeper implanted SD junctions. Effectively raised SDs are achieved without using selective epi. The sidewall spacers also narrow the trench opening below the minimum feature size, and are used to self-align the implanted bottom gate and the high-K/metal top gate.