Some non-resist component contributions to LER and LWR in 193-nm lithography

Improvement of line edge roughness (LER) and line width roughness (LWR) is required for integration of semiconductor devices. This paper describes various process factors affecting LER/LWR of 193 nm resists such as mask layout (bright field/dark field), pitches, optical settings, substrates, film thickness, baking temperature and development condition. The origins of line roughness are discussed in view of aerial image contrast, transmittance of resists and pattern profiles. Bright field mask exhibited lower LER/LWR values than dark field mask, LER/LWR deteriorated as larger pitches and illumination condition affected roughness and these results are explained using normalized image log-slope (NILS). BARC dependence of line roughness is explained by pattern profile difference due to interactions between resist and BARC and in some cases BARC reflectivity. Contributions of film thickness, SB & PEB temperature and development condition to line roughness are also reported.